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lcs700-708 hiperlcs ? family www.powerint.com june 2011 integrated llc controller, high-voltage power mosfets and drivers product highlights features ? llc half-bridge power stage incorporating controller, high and low-side gate drives, and high-voltage power mosfets ? eliminates up to 30 external components ? high maximum operating frequency of 1 mhz ? nominal steady-state operation up to 500 khz ? dramatically reduces magnetics size and allows use of smd ceramic output capacitors ? precise duty symmetry balances output rectifer current, improving effciency ? 50% 0.3% typical at 300 khz ? comprehensive fault handling and current limiting ? programmable brown-in/out thresholds and hysteresis ? undervoltage (uv) and overvoltage (ov) protection ? programmable over-current protection (ocp) ? short-circuit protection (scp) ? over-temperature protection (otp) ? programmable dead-time for optimized design ? programmable burst mode maintains regulation at no-load and improves light load effciency ? programmable soft-start time and delay before soft-start ? accurate programmable minimum and maximum frequency limits ? single package designed for high-power and high-frequency ? reduces assembly cost and reduces pcb layout loop areas ? simple single clip attachment to heat sink ? exposed thermal pad connected to ground potential C no insulators required between package and heat sink ? staggered pin arrangement for simple pc board routing and high-voltage creepage requirements ? paired with hiperpfs pfc product gives complete, high effciency, low part count psu solutions applications ? high-effciency power supplies (80 plus silver, gold and platinum) ? lcd tv power supplies ? led street and area lighting ? printer power supplies ? audio amplifer figure 1. typical application circuit C lcd tv and pc main power supply. description the hiperlcs is an integrated llc power stage incorporating a multi-function controller, high-side and low-side gate drivers, plus two power mosfets in a half-bridge confguration. figure 1 shows a simplifed schematic of a hiperlcs based power stage where the llc resonant inductor is integrated into the transformer. the variable frequency controller provides high effciency by switching the power mosfets at zero voltage (zvs), eliminating switching losses. output power table product maximum practical power 1 lcs700hg 110 w lcs701hg 170 w lcs702hg 220 w lcs703hg 275 w lcs705hg 350 w LCS708HG 440 w table 1. output power table. notes: 1. maximum practical power is the power the part can deliver when properly mounted to a heat sink and a maximum heat sink temperature of 90 c. llc feedback circuit hiperlcs hb vref dt/bf r fmax r burst is fb vcc vcch hv dc input ov/uv g s1/s2 d pi-6159-060211 standby supply control b+ +v rtn b- www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 2 lcs700-708 www.powerint.com figure 2. block diagram. pi-5755-060111 vref ov/uv vsdh/ vsdl vovh/ vovl llc_on llc_clk visf viss vref is feedback (fb) dt/bf 3.4 v regulator uvlo vcc drain (d) hb vcch source (s1/s2) ground (g) + + + + + dead-time generator output control logic debounce 3 llc clock cycles over- temperature protection 7 consecutive llc clock cycles debounce 3 llc clock cycles llc clock level shift uvlo soft-start delay 131,072 llc clock cycles dt/bf resistor sensor bursting thresholds control www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 3 lcs700-708 www.powerint.com pin functional description vcc pin ic power pin. in a typical application, vcc is connected to the 12 v system standby supply via a 5 w resistor. this resistor helps provide fltering and improves noise immunity. note: the system standby supply return should be connected to the b- bus and not to the ground pin. vref pin 3.4 vref pin. an internal voltage reference network used as a voltage source for feedback pin and dt/bf pin pull-up resistor. ground (g) pin g is the return node for all analog small signals. all small signal pin bypass capacitors must be returned to this pin through short traces, with the exception of the d-s high-voltage bypass capacitor, and the vcch bypass capacitor. it is internally connected to the source pins to provide a star connection. do not connect the ground pin to the source pins, nor to the b- bus, in the pcb layout . ov/uv pin overvoltage/undervoltage pin. b+ is sensed by this pin through a resistor divider. the ov/uv pin implements brown-in, brown-out, and overvoltage lockout with hysteresis. pulling this pin down to ground will implement a remote-off function. feedback (fb) pin current fed into this pin determines llc switching frequency; higher current programs higher switching frequency. the pin v-i characteristic resembles a diode to ground during normal switching. an rc network between the vref pin and feedback pin determines the minimum operating frequency, start-up frequency, soft-start time, and delay before start-up. dead-time/burst frequency (dt/bf) pin a resistor divider from vref to ground programs dead-time, maximum switching frequency at start-up, and burst-mode threshold frequencies. current-sense (is) pin the current-sense pin is used for sensing transformer primary current, to detect overload and fault conditions, through a current sense resistor or a capacitive divider plus sense resistor circuit. it resembles a reverse diode to ground, and does not require a rectifer circuit for preventing negative pulses from reaching the pin, provided the reverse current is limited to <5 ma. figure 3. pin numbering and designation. source (s1), (s2) pins source pins of internal low-side mosfet. these should be connected together on the pcb, and connected to the b- from the pfc bulk capacitor or input high-voltage dc return. hb pin this is the output of the half-bridge connected mosfets (source of high-side mosfet, drain of low-side mosfet), to be connected to the llc power train (transformer primary and series resonant capacitor). vcch pin floating bootstrap supply pin for the llc high-side driver. this pin is referenced to the hb pin, which in turn is internally connected to the source pin of the high-side mosfet. a bypass/storage capacitor between vcch and hb pins, and a boot strap diode with a series resistor from the standby supply, are required. the storage capacitor is refreshed every time the lower mosfet turns on or its body diode conducts. drain (d) pin drain pin of the internal high-side mosfet. this connects to the b+ from the pfc bulk capacitor or input high-voltage dc bus. pi-5636-051311 h package (esip-16c) 16 vcc vref g ov/uv fb dt/bf is nc hb d s2 s1 13 vcch 14 11 9 10 8 1 3 4 5 6 7 exposed pad (backside) internally connected to ground pin (see esip-16c package drawing) nc hb g g exposed metal (on package edge) internally connected vcch d d www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 4 lcs700-708 www.powerint.com figure 4. 150 w laser-jet printer power supply. hiperlcs u1 lcs702hg hb vref dt/bf is fb vcc vcch ov/uv g r6 2.2 d1 uf4005 r14 7.5 k r13 86.6 k 1% c19 3.3 nf 200 v c17 2.2 nf 200 v r11 24 r12 220 u2a ltv817a d2 stps30l60ct u2b ltv817a 24 v rtn r10 7.68 k 1% r5 4.7 r18 10 k 1% r23 47 r17 22 k c16 470 f 35 v c15 10 f 35 v c9 22 nf 630 v c14 10 f 35 v l1 150 nh c8 330 nf 50 v c4 4.7 nf 200 v r20 1.2 k r21 4.7 k r19 143 k 1% r8 36.5 k 1% r9 7.68 k 1% 1 fl1 t1 eel25.4 fl2,3 fl4 5 c2 4.7 nf 200 v c1 1 f 25 v c5 4.7 nf 200 v c6 1 f 25 v c20 47 f 35 v c3 220 nf 50 v d3 1n4148 c7 1 nf 200 v c12 47 pf 1 kv c11 6.2 nf 1.6 kv c13 2.2 nf 250 vac u3 lm431aim3dr 2% c10 330 nf 50 v r15 1 k r16 1.5 k r4 20 k 1% r1 976 k 1% r2 976 k 1% r3 976 k 1% s1/s2 d 380 v pi-6160-062011 v cc +12 v control b+ b- www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 5 lcs700-708 www.powerint.com hiperlcs basic operation the hiperlcs is designed for half-bridge llc converters, which are high-effciency resonant, variable frequency converters. the hiperlcs is an llc controller chip with built-in drivers and half-bridge mosfets. llc converters require a fxed dead-time between switching half-cycles. the dead-time, maximum frequency at start-up, and burst threshold frequencies, are programmed with a resistor divider on the dt/bf pin from the vref to the ground pins. the feedback (fb) pin is the frequency control input for the feedback loop. frequency is proportional to feedback pin current. the feedback pin v-i characteristic resembles a diode to ground. burst mode if the frequency commanded by the feedback pin current exceeds the upper burst threshold frequency (f stop , i stop ) programmed by the resistor divider on the dt/bf pin, the output mosfets will turn off, and will resume switching when the current drops below the value which corresponds to the frequency equal to the lower burst threshold frequency (f start , i start ). as a frst approximation, burst mode control resembles a hysteretic controller where the frequency ramps from f start to f stop , stops and repeats. an external component network connected from the vref pin to the feedback pin determines the minimum and start-up feedback pin currents, and thus the minimum and start-up switching frequencies. a soft-start capacitor in this network determines soft-start timing. the vref pin provides a nominal 3.4 v as a reference for this feedback pin external network and other functions. maximum current from this pin must be 4 ma. the dead-time/burst frequency (dt/bf) pin also has a diode-to- ground v-i characteristic. a resistor divider from vref to ground programs dead-time, maximum start-up switching frequency (f max ), and the burst threshold frequencies. the current fowing from the resistor divider to the dt/bf pin determines f max . the ratio of the resistors selects from 3 discrete, burst threshold frequency ratios, which are fxed fractions of f max . the ov/uv pin senses the high-voltage b+ input through a resistor divider. it implements brown-in, brown-out, and ov with hysteresis. the ratios of these voltages are fxed; the user must select the resistor divider ratio such that the brown-in voltage is below the minimum nominal bulk (input) voltage regulation set-point to ensure start-up, and the ov (lower) restart voltage is above the maximum nominal bulk voltage set-point, to ensure that the lcs will restart after a voltage swell event that triggers the ov upper threshold. if different brown-in to brown-out to ov ratios are required, external circuitry needs to be added to the resistor divider. vcc pin uvlo the vcc pin has an internal uvlo function with hysteresis. the hiperlcs will not start until the voltage exceeds the vcc start threshold v uvlo(+) . hiperlcs will turn off when the vcc drops to the vcc shutdown threshold v uvlo(-) . vcch pin uvlo the vcch pin is the supply pin for the high-side driver. it also has a uvlo function similar to the vcc pin, with a threshold lower than the vcc pin. this is to allow for a vcch voltage that is slightly lower than vcc because the vcch pin is fed by a bootstrap diode and series current-limiting resistor from the vcc supply. start-up and auto-restart before start-up the feedback pin is internally pulled up to the vref pin to discharge the soft-start capacitor and to keep the output mosfets off. when start-up commences the internal pull-up transistor turns off, the soft-start capacitor charges, the outputs begin switching at f max , the feedback pin current diminishes, the switching frequency drops, and the psu output rises. when the output reaches the voltage set-point, the optocoupler will conduct, closing the loop and regulating the output. whenever the vcc pin is powered up, the dt/bf pin goes into high impedance mode for 500 m s in order to sense the voltage divider ratio and select the burst threshold. this setting is stored until the next vcc recycle. the dt/bf pin then goes into normal mode, resembling a diode to ground, and the sensed current continuously sets the f max frequency. the burst threshold frequencies are fxed fractions of f max . the internal oscillator runs the internal counters at f max whenever the feedback pin internal pull-up is on. when a fault is detected on the is, ov/uv, or vcc pin (uvlo), the internal feedback pin pull-up transistor turns on for 131,072 clock cycles, to discharge the soft-start capacitor completely, then a restart is attempted. the frst power-up after a vcc recycle only waits 1024 cycles, including the condition where the ov/uv pin rises above the brown-in voltage for the frst time, after vcc is powered up. remote-off remote-off can be invoked by pulling down the ov/uv pin to ground, or by pulling up the is pin to >0.9 v. both will invoke a 131,072 cycle restart cycle. vcc can also be pulled down to shut the device off, but when it is pulled up, the feedback pin is pulled up to the vref pin to discharge the soft-start capacitor for only 1024 f max clock cycles. if this scheme is used, the designer must ensure that the time the vcc is pulled down, plus 1024 cycles, is suffcient to discharge the soft-start capacitor, or if not, that the resulting lower starting frequency is high enough so as not to cause excessive primary currents that may cause the over-current protection to trip. current sense the is pin senses the primary current. it resembles a reverse diode to the ground pin. it is tolerant of negative voltages provided the negative current is limited to <5 ma. therefore it must be connected to the current sense resistor (or primary capacitive voltage divider + sense resistor) via a series current limiting resistor of >220 w . thus it can accept an ac waveform and does not need a rectifer or peak detector circuit. if the is pin senses a nominal positive peak voltage of 0.5 v for 7 consecutive cycles, an auto-restart will be invoked. the is pin also has a second, higher threshold at nominally 0.9 v, which will invoke an auto-restart with a single pulse. the minimum www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 6 lcs700-708 www.powerint.com pulse width requirement for detection of both voltage thresholds is nominally 30 ns. i.e. the thresholds have to be exceeded for >30 ns for proper detection. over-temperature shutdown the hiperlcs has latching otp. vcch must be cycled to resume operation once the unit drops down below the otp threshold. basic layout guidelines the hiperlcs is a high-frequency power device and requires careful attention to circuit board layout in order to achieve maximum performance. the bypass capacitors need to be positioned and laid out carefully to minimize trace lengths to the pins they serve. smd components are recommended for minimum component and trace stray inductance. table 2 describes the recommended bypass capacitor values for pins that require fltering/bypassing. the table lists the pins in the order of most to least sensitive. the bypass capacitor of the pin at the top of the list being the most sensitive, receives higher priority in bypass capacitor positioning to minimize trace lengths, than the bypass capacitor of the pin below it. noise entering the two most sensitive pins on the list, namely the feedback and dt/bf pins, will cause duty cycle, and dead- time imbalance, respectively. figure 5 and figure 6 show two alternate schemes for routing ground traces for optimum performance. figure 5 shows a layout footprint for the lcs with oval pads. these allow a trace to be passed between pins 3 and 5, directly connecting the ground systems for the bypass capacitors located on each side of the ic. figure 6 shows an lcs layout footprint with round pads that do not allow traces to be routed between them due to insuffcient space. in this case, a jumper (jp1, a 1206 size 0 w resistor) is used to connect the ground systems together and allow a connection for pin 3 to be routed under jp1 to the optocoupler. transformer t1 is a source of both high di/dt signals and dv/dt noise. the frst can couple magnetically to sensitive circuitry, while the second can inject noise via electrostatic coupling. electrostatic noise coupling can be reduced by grounding the transformer core, but it is not economically feasible to reduce the stray magnetic feld around the transformer without drastically reducing its effciency. sensitive traces and components (such as the optocoupler) should be located away from the transformer to avoid noise pickup. pin returned to pin recommended value notes feedback (fb) ground 4.7 nf (at 250 khz) increase value proportionally for lower nominal frequency (e.g. 10 nf at 100 khz). forms a pole with feedback pin input impedance which is part of feedback loop characteristic. must not introduce excessive phase shift at expected gain crossover frequency. noise entering feedback pin will cause duty cycle imbalance. dead-time/burst frequency (dt/bf) ground 4.7 nf time constant of this capacitor and the source impedance of the resistors connected to dt/bf pin must be <100 m s. noise entering dt/bf pin will cause dead time imbalance. current sense (is) ground 1 nf (at 250 khz) value changes proportionally with nominal llc stage operating frequency. forms an rc low pass flter with recommended 220 w series resistor. must not attenuate ac signal of primary current sense. vcc ground 1 m f ceramic vref ground 1 m f ceramic vcch hb 0.1 m f - 0.47 m f bootstrap capacitor. provides instantaneous current for high-side driver for turning on high-side mosfet. time constant formed with boost-strap current limiting resistor (in series with bootstrap diode), delays vcch uvlo for a few switching cycles at start-up and during burst mode operation for the frst switching cycles drain (dc bus) s1, s2 10-22 nf smd ceramic minimum, plus 22-100 nf through-hole total of 22 nf per amp of nominal primary rms current. smd part must be located directly at the ic and connected close, with short traces. this prevents ringing of d-s during hard-switching (loss of zvs) transients. it also reduces high-frequency emi. ov/uv ground 4.7 nf table 2. bypass capacitor table in order of importance. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 7 lcs700-708 www.powerint.com figure 5. placement of bypass capacitors on signal pins of ic. figure 6. alternate layout for lcs footprint using round pads with jumper connecting two grounds highlighted. figure 7 shows a an example of preferred routing for the optocoupler and traces connected to the feedback pin. the optocoupler is spaced away from the transformer, reducing noise pickup. the optocoupler output trace (from pin 3) is also routed to increase the distance between it and active components and traces, such as t1 and the hot side of capacitor c12. resistor r20 is located close to u1 rather than optocoupler u2, so that any noise picked up on the optocoupler trace is fltered by the combination of r20 and c4 before it gets to the feedback pin on u1. c4 is placed directly adjacent to the feedback pin of u1 (pin 4). vcch is connected to the standby supply through a high- voltage ultrafast diode and a 2.2 w resistor connected in series. this diode resistor network charges the vcch bypass/storage capacitor whenever the internal llc low-side mosfet is on. the resistor limits the peak instantaneous charging current. see r6 and d1 in figure 8. g pin www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 8 lcs700-708 www.powerint.com figure 8. placement of vcch capacitor. figure 7. preferred routing of optocoupler and traces to feedback pin. small signal bypass capacitors please refer to figure 5 note the location of the small signal bypass capacitors (highlighted) for the feedback, dt/bf, is, vref, ov/uv and vcc pins, which allow short traces to their pin connections and to the ground pin. note that there is no connection between the ground pin and the source pin or the b- bus on the printed circuit board. vcch bypass capacitor please refer to figure 8. note the location of the vcch capacitor (highlighted) which allows short connections to the hb pin and the vcch pin. drain to source high-voltage bypass capacitor please refer to figure 9. note the location of the b+ to b- high- voltage bypass capacitors (highlighted) placed at the ic, minimizing the pcb trace length to the d and s pins. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 9 lcs700-708 www.powerint.com bootstrap circuit and hb node layout please refer to figure 10. note the location of the bootstrap diode, capacitor, resistor, and the hb trace routing. the objective is to keep them away from the small signal components and traces, such as the feedback optocoupler. do not unnecessarily increase the area of the pcb traces on this node, because it will increase the dv/dt (capacitive) coupling to low-voltage circuits. heat sink grounding the exposed metal in the back of the hiperlcs package is internally connected to the ground pin. if the hiperlcs has a dedicated heat sink and there is no electrical insulator between the device and the heat sink, the heat sink should be foating and not electrically connected anywhere else. if the heat sink is shared with other devices in the system, and the heat sink requires grounding to minimize emi, a thin insulator is strongly recommended under the hiperlcs, for improved noise, surge, and system-level esd immunity. the resulting increase in thermal resistance must be considered in the thermal design. transformer secondary the transformer secondary pins, output diodes, and main output capacitors should be positioned close together and routed with short thick traces. this is critical for secondary current symmetry and to minimize output diode inverse voltage stress. the use of ceramic capacitors allows placement between the transformer secondary pins and the output rectifer, producing a very tight layout. see figure 11. the secondary winding halves should be inter-twined together before they are wound on the bobbin. this minimizes the leakage inductance between them and greatly improves current symmetry and minimizes output diode inverse voltage stress. for a 2-output design the half-windings of a given output need to be intertwined. figure 9. placement of b+ and b- high-voltage bypass capacitors. source drain www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 10 lcs700-708 www.powerint.com figure 11. placement of capacitors between transformer secondary pins and the output rectifer to minimize and equalize loop areas. figure 10. placement of boot strap diode, capacitor, resistor and the high-voltage trace routing. center tap secondary secondary output capacitors rectifer transformer primary high-side www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 11 lcs700-708 www.powerint.com key design details the llc converter is a variable frequency resonant converter. as input voltage decreases, the frequency must decrease in order to maintain output regulation. to a lesser extent, as load reduces the frequency must increase. when the converter is operating at the series resonant frequency, the frequency changes very little with load. the minimum operating frequency required occurs at brownout (minimum input voltage), at full load. operating frequency selection for lowest cost, and smallest transformer size with the least amount of copper, the recommended nominal operating frequency is ~250 khz. this allows the use of low-cost ceramic output capacitors in place of electrolytic capacitors, especially at higher output voltages (12 v). if the core and bobbin used exhibits too much leakage inductance for 250 khz, operation at 180 khz also results in excellent performance. for optimal effciency at 250 khz, awg #44 (0.05 mm) litz is recommended for the primary, and awg #42 (0.07 mm) for the secondary winding. thicker gauge lower cost litz can be used at the expense of increased copper loss and lower effciency. litz gauge (awg #38 or 0.1 mm) is optimal for very low frequencies (60-70 khz), requires much larger transformers and greater lengths of litz wire. for nominal operating frequencies even as low as 130 khz, the use of pc44 or equivalent core material is recommended for reduced losses. for a given transformer design, shifting the frequency up (by substituting a smaller resonant capacitor), will reduce core loss (due to reduced ac fux density b ac ) and increase copper loss. core loss is a stronger function of fux density than of frequency. the increased frequency increases copper loss due to eddy current losses. nominal operating frequencies >300 khz start to lose signifcant effciency due to increased eddy current losses in the copper, and due to the fact that a more signifcant percentage of time is spent on the primary slew time (zvs transition time) which erodes the percentage of time that power is transferred to the secondary. resonant tank and transformer design please refer to the application note an-55 for guidance on using the pixls hiperlcs spreadsheet which assists in the entire design process. primary inductance the optimal powertrain design for the hiperlcs uses a primary inductance that results in minimal loss of zvs at any steady- state condition. some loss of zvs during non-steady-state conditions is acceptable. reducing primary inductance produces higher magnetizing current which increases the range of zvs operation, but the increased magnetizing current increases losses and reduces effciency. the calculation of the primary inductance to be used for a frst-pass design is based on device size, rated load, minimum input voltage, and desired operating frequency. it is provided in the pixls spreadsheet. l pri is the primary inductance of an integrated transformer (high leakage inductance), or in the case of the use of an external series inductance, the sum of this inductance and the transformer primary inductance. leakage inductance the parameter k ratio is a function of leakage inductance: k l l 1 rati o re s pr i =- the recommended k ratio is from 2.5 - 7. this determines the acceptable range of leakage inductance. l res is the leakage inductance in an integrated transformer; if a separate series inductor is used, it is the sum of this inductance and the leakage inductance of the transformer. a low k ratio (high leakage inductance) may not be capable of regulation at the minimum input voltage, and may show increased transformer copper losses due to the leakage fux. a high k ratio (low leakage inductance) will have high peak and rms currents at low-line, and require a lower primary inductance to achieve zvs operation over a suitably wide range, which increases the resonant circulating current, reducing effciency. the core and bobbin designs available to the designer may limit the adjustability of leakage inductance. fortunately, excellent performance can be achieved over a relatively wide range of leakage inductance values. the k ratio directly affects the frequency range that the llc needs to operate in order to maintain regulation over the input voltage range. increasing k ratio increases this frequency range, lowering f min . a low f min is only a potential problem for low frequency designs which typically run at higher nominal b ac . this may allow the core to reach saturation when operating at f min . operating at f min occurs when the input voltage is at a minimal (input brown-out). for a design with a separate resonant inductor, running the inductance on the low side of the range (k ratio = 7), minimizes the size and cost of the inductor. adjusting leakage inductance sectioned bobbins (separated primary and secondary) are commonly used for llc converters. increasing or decreasing both primary and secondary turns (while maintaining turns ratio) will change the leakage inductance proportionally to the square of primary turns. if the leakage inductance is too high, one possible solution is to use a 3-section bobbin, where the secondary is in the middle section, and the primary winding is split into 2 halves connected in series. lastly, if the leakage inductance is too low an external inductor may be added. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 12 lcs700-708 www.powerint.com resonant frequency the series resonant frequency is a function of l res and c res , the resonant capacitor. for any given value of l res , the value of c res can be adjusted for the desired series resonant frequency f res . for best effciency the resonant frequency is set close to the target operating frequency at nominal input voltage. operating frequency and frequency ratio the operating to resonant frequency ratio f ratio is defned as: f f f rati o re s sw = f ratio = 1 signifes the converter is operating at the series resonant frequency. the main determinant of f ratio is the transformer turns ratio. increasing primary turns lowers f ratio for a given input and output voltage. the recommended f ratio at nominal input voltage is 0.92 C 0.97. operating at resonance often yields the highest effciency for the resonant powertrain if output rectifer selection is ignored. however, operating slightly below resonance (which puts the rectifers in discontinuous conduction mode), allows the use of lower voltage diodes or synchronous mosfets, which have lower losses, increasing overall effciency. this is because at high-line, when the converter needs to operate above resonance, the rectifers operate less deeply in continuous mode, reducing the magnitude of their current commutation, reducing their stray inductance voltage spikes. (the stray inductance is comprised of the leakage inductance between secondary phases and the stray inductance in the connections to the rectifers and output capacitors). conversely, operating at a very low f ratio (<0.8) results in higher rms and peak currents. in some cases, this may result in an optimal design because it allows the use of lower voltage rating, lower v f rectifer as they do not operate in continuous conduction mode even at high-line, results in no voltage spikes enabling a lower voltage rating. an llc half-bridge converter will operate at resonance when this equation is true: out v v n 2 in eq = where n eq is the transformer equivalent circuit turns ratio. note that the n eq of an integrated transformer is lower than its physical turns ratio n pri / n sec . the secondary turns is that of each half-secondary. v out in the above equation is equal to output voltage + diode drop. the divisor 2 is due to the half-bridge confguration C each half-cycle conducts half the input voltage to each secondary half. note that if the resonant capacitor or inductance value is changed, both switching frequency and resonant frequency change, but f ratio changes little. for a given design, the input voltage at which the llc operates at resonance is v input(resonance) . below this voltage, the llc operates at a lower frequency (below resonance). thus for the recommended f ratio 0.95 at nominal input voltage, v input(resonance) will be slightly higher than the nominal voltage. for a design with a variable nominal input voltage (e.g. no pfc pre-regulator), it is recommended that the initial turns ratio be set so that v input(resonance) is at about halfway between maximum and minimum input voltage. for a design with a variable output voltage (e.g. constant current regulated output), it is recommended that the initial turns ratio be set to operate the llc at resonance at a point halfway between minimum and maximum output voltages. dead-time selection the vast majority of designs using hiperlcs, regardless of power and operating frequency, work very well with a dead-time of between 290 and 360 ns. designs that require a low v brownout tend to require shorter dead-times. the dead-time setting is a compromise between low-line / full load (low frequency), and minimum-load / high-line (high- frequency) conditions. low-line / full load operation has short optimal dead-times, while minimum load / high-line has long optimal dead-times. a dead-time setting that is longer than optimal for low-line / full load operation, exhibiting partial loss of zvs, is acceptable if the condition does not occur during steady-state operation C i.e. appears only during transient conditions, such as hold-up time. operation with loss of zvs during steady-state operation leads to high internal power dissipation and should be avoided. a dead-time setting that is shorter than optimal for high-line / minimum-load operation, will tend to cause the feedback sign to invert and force the hiperlcs to enter burst mode. this is acceptable if the resulting burst mode operation is acceptable (i.e. repetition rate does not produce audible noise and if the large signal transients, wherein the hiperlcs enters and exits burst mode, is acceptable). note that with a pfc pre-regulated front end, a load dump (e.g. 100% to 1% load step) will exhibit a transient input voltage condition only temporarily (e.g. input voltage to llc stage will increase from 380 v to 410 v and relatively slowly return to 380 v). note also that the burst threshold frequency setting is another variable available to the designer to tune burst mode. ov/uv pin the hiperlcs ov/uv pin which monitors the input (b+) voltage, has a brown-out shutdown threshold (v sd(l) ) of nominally 79% of the brown-in (turn-on) threshold (v sd(h) ), which in turn, is nominally 2.4 v. the overvoltage (ov) lockout shutdown threshold (v ov(h) ) is nominally 131% of the brown-in start-up threshold, and the ov restart point (v ov(l) ) at nominally 126%. the ratios of these thresholds are fxed and selected for maximum utility in a design with a pfc pre-regulator front-end with a fxed output voltage set-point. the resistor divider ratio has to be selected so that brown-in point is always below the pfc output set-point, and so that the ov restart (lower) threshold, is always above it, including component tolerances. during hold-up time, the voltage will drop from the nominal value, down to the brown-out threshold, whereby the hiperlcs will stop switching. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 13 lcs700-708 www.powerint.com if the input voltage is variable (e.g. no pfc pre-regulator), and the variation is greater than 24%, the ov threshold should be increased with external circuitry on the resistor divider. external circuitry is also needed if v brownout needs to be reduced below the default ratio. in the example in the left-hand side of figure 14 the resistor divider is set so that brown-in threshold is 376 v, just under the v pfc set-point of 385 v. the ov shutdown threshold is 495 v, which gives adequate margin against the device max v ds rating of 530 v. this minimizes required minimum llc gain, and minimizes the peak current at brown-out. in the example on the right of figure 14, the ov restart threshold is set to 418 v, just above v pfc . this maximizes hold-up time for a given bulk capacitor value. the ov/uv pin has an integrated 5 m w pull-down to detect pin-open fault conditions. the recommended pull-down resistor value for the ov/uv pin divider is 20 k w - 22 k w . a very large resistor value will cause the pin pull-down current to affect accuracy, and a small value will increase power loss. dt/bf pin the dt/bf pin senses the voltage divider ratio by entering into a high-impedance mode for 500 m s after vcc is applied. it senses the pin voltage, before the hiperlcs starts switching. see figure 15. there are 3 discrete burst threshold settings that can be selected. (this determines the burst start and stop switching frequencies, see table 3). for proper selection, set the ratio of r burst to r fmax as per table 3. table 3. burst threshold selection table. the burst threshold setting is stored until vcc is powered down. after the burst threshold detection, the dt/bf pin operates in normal mode, sinking current, resembling a diode to ground, with a thevenin equivalent circuit of nominally 0.66 v and 1.1 k w . the current from the resistor divider into the pin, determines the dead-time and the maximum frequency f max . the relationship between dead-time and f max is fxed and approximated by: time - f khz dead ns 27 00 0 0 max = ^ ^ h h the relationship between dt/bf pin current and f max , and switching frequency vs. feedback pin current (which has the same characteristic), is show in figure 16. the burst mode start and stop frequency thresholds are fxed fractions of f max , which depend on the burst threshold setting, as set by the resistor divider ratio on the dt/bf pin. table 4. burst start and stop frequencies as ratios of f max . figure 14. ov/uv pin voltage thresholds, at minimum and maximum divider ratios, for 385 v nominal input voltage. 495 v vovh 376 v vsdh 298 v vsdl 475 v vovl ov/uv pin resistor divider chosen for minimum required llc gain 200 v time time 385 v 436 v vovh 331 v vsdh 262 v vsdl 418 v vovl ov/uv pin resistor divider chosen for minimum hold-up capacitance 200 v 385 v pi-6154-051811 r fmax r burst gnd vref dt/bf pi-6460-051811 figure 15. dt/bf pin divider. burst threshold r burst / r fmax 1 19 2 9 3 5.67 burst threshold setting f start /f max f stop /f max 1 7/16 8/16 2 6/16 7/16 3 5/16 6/16 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 14 lcs700-708 www.powerint.com for example, if bt2 is selected, and f max is 800 khz, then f start = 300 khz, and f stop = 350 khz. if during normal operation the load is reduced and the frequency rises to 350 khz, the switching will stop. this causes the output voltage to drop and the feedback loop to decrease the feedback pin current. when the current decreases to a value which corresponds to 300 khz, switching will commence, and the cycle will repeat. during start-up mode, however, the outputs can switch at a frequency between f stop and f max (250 khz and 800 khz in the above example). start-up mode is exited once the switching frequency drops below f stop , and the hiperlcs will subsequently enter burst mode if the feedback loop attempts to produce a switching frequency >f stop . f max is the frequency at which the internal counters run when the hiperlcs is in the off-state of the auto-restart cycle, or in the power-up delay before switching. the minimum recommended dead-time is 275 ns, and thus the maximum f max setting is 1 mhz. to simplify the selection of r fmax , see the selection curves in figure 17. figure 16. feedback pin and dt/bf pin current vs. frequency. pi-6150-052011 600 400 200 0 800 1000 0 50 150 100 200 250 300 350 400 450 frequency (khz) current (a) 250 300 350 400 500 450 dead-time (ns) r fmax (k) 13.0 12.0 11.0 9.0 10.0 8.0 7.0 6.0 5.0 pi-6458-051911 bt1 bt2 bt3 figure 17. r fmax vs. dead-time, for the 3 different burst threshold settings. figure 18. f start (lower burst threshold frequency) vs. dead-time setting for different burst threshold settings (bt1, bt2, bt3). 250 300 350 400 500 450 dead-time (ns) f start (khz) 500 450 350 400 300 250 200 150 pi-6457-051911 bt1 bt2 bt3 the f stop to f start ratio is fxed, and dependent on the burst threshold setting (see table 5). table 5. ratio of f stop /f start vs. burst threshold selection. as a frst approximation, during burst mode, the frequency ramps from f start to f stop ; then switching stops, and then the cycle repeats. feedback pin the feedback pin is the voltage regulation feedback pin. it has a nominal thevenin equivalent circuit of 0.65 v and 2.5 k 1 . in normal operation, it sinks current. during the off-period of auto-restart, and during the clocked delay before start-up, it pulls up internally to v ref in order to discharge the soft-start capacitor. the current entering the pin determines switching frequency. higher current yields higher frequency and thus reduces llc output voltage. in a typical application an optocoupler connected to the vref pin pulls up on the feedback pin, via a resistor network. the optocoupler is confgured to source increasing feedback pin current, as the output rises. the resistor network between the optocoupler, feedback pin, and vref pin, determine the minimum and maximum feedback pin current (and thus the minimum and maximum operating frequency), that the optocoupler can command as it goes from cutoff to saturation. this network also contains the soft-start timing capacitor, c start (figure 19). the minimum frequency as set by this network must be lower than the frequency required by the powertrain at minimum input voltage. in figure 19 this is determined by the sum of r fmin and r start . the feedback pin current is determined by these two resistors when the optocoupler is cut off. c start can be ignored during normal operation. do not confuse r start , which determines burst threshold setting f stop / f start 1 1.14 2 1.17 3 1.20 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 15 lcs700-708 www.powerint.com start-up frequency, and f start , which is the burst mode start (lower) threshold frequency. the feedback pin current at start-up is determined by the value of r start because the voltage on c start will be zero. for minimum start-up peak currents, this current should match or slightly exceed the dt/bf pin current so that start-up switching frequency begins at f max . the resulting value of r start will be approximately 10% lower than the value of the pull-up resistor on the dt/bf pin. the frequency will slide down as c start charges. if r start is smaller than that which provides start-up at f max , it will create an additional delay before start-up switching. please see the pixls hiperlcs spreadsheet. resistor r load provides a load on the optocoupler, and speeds up the large signal transient response during burst mode. the recommended value is ~4.7 k w . diode d1 prevents r load from loading r fmin when the optocoupler is cut off. diode d1 can be omitted and a combination of resistor values found to achieve the desired f min but the resulting tolerances will be poor. resistor r opto will improve the esd and surge immunity of the psu. it also improves burst mode output ripple voltage. its maximum value must be such that the feedback pin current is equal to the dt/bf pin current when the optocoupler is in saturation and the feedback pin is at 2.0 v (please see pixls hiperlcs spreadsheet). this is to ensure that if the hiperlcs does not exit start-up mode, because the feedback loop did not allow the switching frequency to drop below f stop , then it can regulate at light load by bursting at f max . note however bursting at f max can lead to high internal dissipation due to loss of zvs and should be avoided . see figure 20. capacitor c start should be sized at the minimum possible value that exhibits a 7 consecutive-cycle peak current at start-up that is just below the peak current measured at brown-out and full load. a larger value will slow down start-up and will make it more likely that f stop is not reached. this can prevent exiting start-up mode when the hiperlcs is powered up at high-line and minimum load, and may subsequently cause the hiperlcs to burst at f max instead of between f start and f stop . figure 19. feedback network shown with additional load resistor. ~850 khz 10 s / div i pri 850 ns / div severe loss of zvs bursting duty 50% pi-6463-06071 1 v hb figure 20. bursting at f max causes high internal dissipation due to loss of zvs and should be avoided. r fmin r start r opto d1 r load 3.4 v u1b c start c fb 4.7 nf gnd vref fb pi-6118-051711 figure 21. vref to fb external resistance vs. frequency. in order to calculate r fmin and r start , use the following equation which describes nominal resistance from feedback pin to vref pin, vs. frequency: r 3574 .. fb lo gf 06 04 10 119 3 = # + f ^ ^h h where r fb is in k w and f is in khz. to calculate the minimum r start , which produces start-up at f max , use the above equation with f = f max from the equation relating dead-time and f max . to set f min , use the above equation with f = f min 0.93. where 0.93 is to ensure that, despite the worst case frequency tolerance of -7%, the frequency can go below f min , guaranteeing regulation at v brownout . using the resulting calculated value for r fb , calculate r fmin : rr r fmin fb start =- the sum of r fmin and r start determines f min . 50 100 20 200 500 1000 4 10 20 50 100 300 r fb (k ) frequency (khz) pi-6151-06091 1 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 16 lcs700-708 www.powerint.com it should be noted that the 4.7 nf decoupling capacitor, c fb (see figure 19), in conjunction with the 2.5 k w input resistance presented by the feedback pin, form a pole in the llc transfer function. this can add signifcant phase lag to the feedback loop. a typical value for a 250 khz design with a 3 khz crossover frequency is 4.7 nf. to prevent loop instability, the value of the 4.7 nf capacitor should not be increased arbitrarily. at the other extreme, insuffcient feedback pin bypass capacitance or poor layout may cause duty cycle asymmetry. start-up and auto-restart at start-up and during the off-state of the auto-restart cycle, the feedback pin is internally pulled up to the vref pin. this keeps the output mosfets off and discharges the soft-start capacitor, in preparation for soft-start. at start-up, this state remains for 1024 clock cycles at frequency f max . during the off-state of auto-restart, or if the ov/uv or is pin is triggered while the vcc remains above its uvlo threshold, this state remains for 131,072 clock cycles. after 1024 or 131,072 cycles (as the case may be), the hiperlcs turns off the internal pull-up transistor, the soft-start capacitor begins to charge, the output mosfets switch at f max , current in the feedback pin diminishes, the frequency begins to drop, and the psu output rises. for example, for f max = 800 khz, the start-up delay after vcc power-up is 1.3 ms. if is, or the ov/uv pin are tripped, auto- restart is invoked, with a restart delay of 164 ms. the feedback pin has a current limit equal to the current fowing into the dt/bf pin. this limits the maximum current that charges the soft-start capacitor at start-up. if r start is smaller than that which allows the feedback pin current to match the dt/bf pin current at start-up, an additional delay is introduced. c start will charge at the current limit, and switching will only commence when the feedback pin voltage drops below 2.0 v. thus the designer can add an additional start-up delay if desired. as the soft-start capacitor continues to charge, the current through r start and thus the feedback pin decreases, reducing switching frequency. the output voltage climbs; and when the feedback loop closes, the optocoupler conducts and starts controlling the switching frequency thus the output voltage. remote-off remote-off can be invoked by pulling down the ov/uv pin to ground, or by pulling up the is pin to >0.9 v. both will invoke a 131,072 cycle restart cycle. vcc can also be pulled down to shut the device off, but when it is pulled up, the feedback pin is pulled up to the vref pin to discharge the soft-start capacitor for only 1024 f max clock cycles. if this scheme is used, the designer must ensure that the time the vcc is pulled down, plus 1024 cycles, is suffcient to discharge the soft-start capacitor, or if not, that the resulting lower starting frequency is high enough so as not to cause excessive primary currents that may cause the over-current protection to trip. is pin the is pin has 2 thresholds: nominally 0.5 v and 0.9 v. the is pin can tolerate small negative voltages and currents, and thus does not need a peak detector or rectifer circuit. the pin has a reverse-biased diode to ground equivalent circuit, and can tolerate a maximum negative current of 5 ma. the primary current is sampled by a primary, b- referenced current sense resistor, or by a capacitor current divider + current sense resistor combination circuit. in order to limit the negative current to 5 ma, a current limiting resistor between the sense resistor and the is pin is necessary, with a minimum value of 220 w . using the minimum value maximizes the is pin bypass capacitor value and thus pin noise rejection, for a given rc pole frequency. the is pin will invoke a restart if it sees 7 consecutive pulses >0.5 v. it will also invoke a restart if a single pulse exceeds 0.9 v. the minimum pulse detection time is nominally 30 ns C i.e. the pulses must be higher than the threshold voltage for >30 ns. the capacitive divider circuit in figure 23 reduces power dissipation and improves effciency over a simple current sense resistor circuit. the two capacitors, main resonant capacitor c11, and sense capacitor c12, form a current divider. the portion of the primary current routed through c12 is cc c 11 12 12 + . consequently, the voltage at the is pin is equal to ## i cc c r 11 12 12 11 p + , where i p is the primary current fowing from the hb pin through the transformer primary. the current in the sense capacitor passes through sense resistor r11. resistor r11 is the main means for tuning current limit. the signal on r11, an ac voltage, passes through low-pass flter r12 and c7, to the is pin. note that r11 is returned to the ground pin and not to source pin. pi-6471-05241 1 2.5 2 1.5 1 0 0.5 3 3.5 4 4.5 5 -6 0 -2 2 -4 ti me (ms) amps (a) v olts (v) 4 6 -8 -10 20 50 40 60 30 70 80 10 0 primary current output v oltage b a figure 22. typical start-up waveform. observe initial current spike a to ensure it is below the 1-cycle current limit. a higher f max reduces it. size the soft-start capacitor so that the peak of b is just below the peak current at v brownout at full load. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 17 lcs700-708 www.powerint.com the recommended series resistor value of 220 w and the bypass capacitor form a low-pass flter, and its time constant must not cause signifcant attenuation of the current sense signal at the nominal operating frequency. the effect of the attenuation is greatest for the frst pulse in the start-up current waveform, and can also affect proper shutdown during short-circuit testing, which typically trips the 7-cycle current limit. place a close- coupled probe across the is pin bypass capacitor and compare the waveform to the primary current. burst mode operation and tuning burst mode will produce a typical waveform such as in figure 24. during the burst pulse train, the switching frequency rises from f start to f stop . if the initial output ripple spike at the beginning of the burst pulse train is ignored, the output ripple somewhat resembles a sawtooth. see the output ripple waveform in figure 24. when the hiperlcs is switching, the output rises. when it stops switching, the output falls. the top of the sawtooth is where the burst pulse train ends, because the feedback loop has commanded a frequency = f stop . the bottom of the sawtooth is where the burst pulse train begins, because the feedback loop has commanded a frequency = f start . as such, the burst mode control resembles a hysteretic controller, where the top and bottom of the sawtooth are fxed by the feedback loop gain. the downward slope of the sawtooth is merely the output capacitors discharging into the load, with dv/dt: # ic dt dv = where i = load current. c is the total output capacitance. the upward slope of the sawtooth is dependent on the difference between the current delivered by the powertrain, and the current drawn by the load. for a given design, the upward slope increases with input voltage. the burst repetition rate (frequency) then increases with load. when the load reaches a point where the powertrain can regulate at a frequency rev. b 062011 18 lcs700-708 www.powerint.com pi-6470-06281 1 0 50 100 100 400 300 200 ti me (s) hb v oltage (v) 0 -5 output ripple v oltage (v) 24.0 23.9 24.1 figure 26. zoom in of last few switching cycles of burst pulse train of figure 24. the switching frequency of the last few cycles is f stop , 383 khz in this case (arrow). the ringing in v hb after switching stops, is the primary inductance ringing with the mosfet capacitance. higher f start will decrease the load threshold at which bursting begins, increase the input voltage threshold and decrease the output ripple in burst mode, but will increase the burst repetition rate, which may introduce audible noise in some combinations of line and load. the choice of f start will affect the large signal transient response where the hiperlcs goes in and out of burst mode. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 19 lcs700-708 www.powerint.com parameter symbol conditions source = 0 v; t j = 0 to 100 c v cc = 12 v, v cch = 12 v (unless otherwise specifed) min typ max units half-bridge off-state current i dss measured from d to hb or from hb to s t j = 100 c, v cc = 12 v, v cch = 12 v, v d = 424 v lcs700 60 m a lcs701 60 lcs702 65 lcs703 80 lcs705 120 lcs708 200 on-state resistance r ds(on) measured from d to hb or from hb to s v cc = 12 v, v cch = 12 v, t j = 25 c lcs700, i = 0.8 a 1.53 1.82 w lcs701, i = 1.2 a 1.00 1.24 lcs702, i = 1.6 a 0.74 0.92 lsc703, i = 2.0 a 0.60 0.73 lcs705, i = 3.0 a 0.40 0.49 lcs708, i = 4.8 a 0.26 0.31 thermal resistance junction to case thermal resistance (1,3) : lcs700 ( q jc )...................................... ...... 7. 6 c/w lcs701 ( q jc ).............................. ............. 7. 0 c/w lcs702 ( q jc ).............................. ............. 6.6 c/w lcs703 ( q jc ) ...................................... 6.2 c/w lcs705 ( q jc )............................... ............ 5.9 c/w lcs708 ( q jc )............................... ............ 5.5 c/w junction to heat sink thermal resistance (1,2) : lcs700 ( q jh )............................... .......... 10.1 c/w lcs701 ( q jh )...................................... ...... 9.5 c/w lcs702 ( q jh )............................... ............ 9.1 c/w lcs703 ( q jh )............................... ............ 8.7 c/w lcs705 ( q jh )............................... ............ 8.4 c/w lcs708 ( q jh )............................... ............ 8.0 c/w hottest junction to ot sensor thermal offset (1,2,4) : lcs700 ( t j-ot )........................................ 4.6 c/w lcs701 ( t j-ot )............................... ........ 4.0 c/w lcs702 ( t j-ot )................................ ....... 3.5 c/w lcs703 ( t j-ot ) .................................. 3.2 c/w lcs705 ( t j-ot )................................ ....... 2.8 c/w lcs708 ( t j-ot )................................ ....... 2.5 c/w notes: 1. both power switches each dissipating half the total power. 2. mounted to an aluminum heat sink with uniform coverage of thermalloy thermal paste. mounting clip with normal force >30 n applied to the center of the package. 3. junction to case thermal resistance is based on hottest junction, case temperature measured at center of package back surface. 4. temperature difference between hottest junction and over- temperature sensor. 5. thermal resistance values are preliminary and subject to change. absolute maximum ratings instantaneous repetitive d or hb current (5) .............................. .................................. v cc , v cch = 11.5 v, 25 c lcs700................................ ........................ 5.2 a lcs701............................. ............................ 7.7 a lcs702.............................. ........................ 10.3 a lcs703 ................................................. 12.9 a lcs705............................... ....................... 19.3 a lcs708............................... ....................... 30.9 a instantaneous repetitive d or hb current (5) ............................... ...................... v cc , v cch = 11.5 v, 125 c lcs700............................... ......................... 4.2 a lcs701............................ ............................ 6.2 a lcs702.............................. .......................... 8.3 a lcs703 ................................................. 10.4 a lcs705............................... ....................... 15.6 a lcs708...................................... ................. 24.9 a drain pin voltage d (1) ......................................... -1.3 v to 530 v half-bridge voltage, hb (1) ............................... -1.3 v to d + 0.5 v half-bridge voltage slew rate, hb ............................. ....... 10 v/ns supply pin voltage, vcc (1) , vcch (2) .........................-0.3 v to 15 v g pin voltage (1) .................................................... -0.3 v to 0.3 v is pin voltage (3) ...................................... ...... -0.65 to vref + 0.3 v dt/bf and feedback pin voltages (3) ....... -0.3 to vref + 0.3 v ov/uv pin voltage (3) .................................... -0.3 to vcc + 0.3 v pin current (vref, ov/uv, dt/bf, feedback, is)....... . 100 ma junction temperature ...................................... -40 c to 150 c storage temperature ...................................... -65 c to 150 c lead temperature (4) ......................................................... 260 c esd rating (jesd22-a114-b, hbm) .................................... 2 kv notes: 1. voltage referenced to s. 2. voltage referenced to hb. 3. voltage referenced to g. 4. 1/16 inch from case for 5 seconds. 5. one-cycle peak current can exceed repetitive maximum current for t < 460 ns if t j < 100 c and drain voltage 400 vdc. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 20 lcs700-708 www.powerint.com parameter symbol conditions source = 0 v; t j = 0 to 100 c v cc = 12 v, v cch = 12 v (unless otherwise specifed) min typ max units half-bridge (cont.) on-state resistance r ds(on) measured from d to hb or from hb to s v cc = 12 v, v cch = 1 2 v, t j = 100 c lcs700, i = 0.8 a 2.15 2.63 w lcs701, i = 1.2 a 1.42 1.78 lcs702, i = 1.6 a 1.05 1.33 lcs703, i = 2.0 a 0.85 1.06 lcs705, i = 3.0 a 0.58 0.71 lcs708, i = 4.8 a 0.36 0.45 half-bridge capacitance c hb effective half-bridge capacitance. v hb swinging from 0 v to 400 v or 400 v to 0 v, see note a lcs700 134 pf lcs701 201 lcs702 268 lcs703 335 lcs705 503 lcs708 804 diode forward voltage v fwd measured from hb to d or from s to hb t j = 125 c lcs700, i = 0.8 a 1.15 v lcs701, i = 1.2 a 1.15 lcs702, i = 1.6 a 1.15 lsc703, i = 2.0 a 1.15 lcs705, i = 3.0 a 1.15 lcs708, i = 4.8 a 1.15 power supply vcc supply voltage range v cc see note c 11.4 12 15 v vcch supply voltage range v cch see note c 11.4 12 15 v start-up current i cc(off) undervoltage lockout state: v cc = 8 v 0.85 1 ma inhibit current i cc(inhibit) v cc = 12 v, ov/uv < v sd(l) 1.35 1.7 ma vcc operating current i cc(on) typical at v cc = 12 v maximum at v cc = 15 v measured at 300 khz, hb open and v d = 15 v lcs700 4.0 5.2 ma lcs701 4.4 5.8 lcs702 4.9 6.5 lcs703 5.4 7.1 lcs705 6.6 8.8 lcs708 8.8 11.8 vcch operating current i cch(on) typical at v cch = 12 v maximum at v cch = 15 v measured at 300 khz, hb open and v d = 15 v lcs700 3.4 4.6 ma lcs701 3.9 5.2 lcs702 4.3 5.8 lsc703 4.7 6.4 lcs705 5.8 7.9 lcs708 7.8 10.7 vcc supply undervoltage lockout vcc start threshold v uvlo(+) device exits uvlo state when v cc exceeds uvlo+ 10 10.7 11.4 v vcc shutdown threshold v uvlo(-) device enters uvlo state when v cc falls below uvlo+ 9.1 9.8 10.5 v vcc start-up/shut - down hysteresis v uvlo(hyst) 0.70 0.90 1.20 v www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 21 lcs700-708 www.powerint.com parameter symbol conditions source = 0 v; t j = 0 to 100 c v cc = 12 v, v cch = 12 v (unless otherwise specifed) min typ max units vcch supply undervoltage lockout vcch start threshold v uvlo(h+) driver exits uvlo state when v cch exceeds uvloh+ 8.2 8.5 8.9 v vcch shutdown threshold v uvlo(h-) driver enters uvlo state when v cch falls below uvloh- 7.4 7.5 8.1 v vcch start-up/ shutdown hysteresis v uvlo(h)hyst 0.65 0.75 1.00 v high-voltage supply undervoltage/overvoltage enable ov/uv overvoltage shutdown threshold v ov(h) overvoltage assertion threshold 129 131 133 % of v sd(h) ov/uv overvoltage recovery threshold v ov(l) overvoltage de-assertion threshold 124 126 128 % of v sd(h) ov/uv undervoltage start threshold v sd(h) undervoltage de-assertion threshold 2.35 2.40 2.45 v ov/uv undervoltage shutdown threshold v sd(l) undervoltage assertion threshold 77 79 81 % of v sd(h) ov/uv pin input resistance r in(ovuv) ov/uv pin resistance to g 3.0 5.0 6.6 m w reference reference voltage v ref i ref = 4 m a 3.25 3.40 3.50 v current source capability of vref pin i ref 4 ma v ref capacitance c ref required external coupling on vref pin 1 m f llc oscillator frequency range f range 25 1000 khz accuracy of minimum frequency limit f min(acc) r fb = 37.9 k w to v ref , 180 khz -5.0 5.0 % f min(acl) r fb = 154 k w to v ref , 50 khz -7.5 7.5 accuracy of maximum frequency limit f max(acc) i fb = i dt/bf , r fmax = 12.5 k w , f max = 510 khz -7.5 7.5 % duty balance d llc duty symmetry of the half-bridge wave - form, c fb = 4.7 nf, c dt/bf = 4.7 nf, 250 khz. use recommended layout 49 51 % dead-time b t d r fmax = 7 k w, r burst = 39.6 k w 330 ns dt/bf control current range i dt/bf 30 430 m a i fb threshold to stop llc switching i stop1 threshold applies after exiting soft-start mode for burst setting bt1 49.8 % of i dt/bf i stop2 threshold applies after exiting soft-start mode for burst setting bt2 43.9 i stop3 threshold applies after exiting soft-start mode for burst setting bt3 37.1 www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 22 lcs700-708 www.powerint.com parameter symbol conditions source = 0 v; t j = 0 to 100 c v cc = 12 v, v cch = 12 v (unless otherwise specifed) min typ max units llc oscillator (cont.) i fb threshold hysteresis i burst(hyst) i start is i burst(hyst) below i stop 5 6.25 8 % of i dt/bf dt/bf voltage to program burst setting v bt1 required v dt/bf at start-up to enable burst setting bt1 93.5 95 96.3 % of v ref v bt2 required v dt/bf at start-up to enable burst setting bt2 88.5 90 91.3 v bt3 required v dt/bf at start-up to enable burst setting bt3 83.5 85 86.3 time constant for the combination of r fmax , r burst and the decoup- ling cap on dt/bf rc dt/bf this time constant must be less than the specifed maximum to ensure correct setting of burst mode. 100 m s fb current maximum i fb determines the maximum control frequency that can be set by i fb . 100 %i dt/bf fb control current range i fb i fb is limited by the current into dt/bf 15 430 m a fb virtual voltage v fb fb input appears as r in(fb) in series with v fb . 30 m a < i fb < i dt/bf 0.65 v fb input resistance r in(fb) fb input appears as r in(fb) in series with v fb . 30 m a < i fb < i dt/bf 2.5 k w fb input resistance during soft-start r fb(ss) fb input appears as r fb(ss) in series with v ref during the soft-start delay interval or when ov/uv < v sd or ov/uv > v ov 750 w over-current protection fast over-current fault voltage threshold 4 v is(f) 0.855 0.905 0.955 v slow over-current fault voltage threshold v is(s) 7 llc clock cycle debounce 0.455 0.505 0.555 v over-current fault pulse width t is minimum time v is exceeds v is(f) /v is(s) per cycle to trigger fault protection 30 ns over-temperature protection over-temperature shutdown threshold a t ot 140 c notes: a. guaranteed by design. b. typical apparent dead-time at the hb pin under resonant zvs conditions. c. vcc/vcch operating range to achieve power capabilities specifed in data sheet power table. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 23 lcs700-708 www.powerint.com pi-6183-112910 400 500 300 20 100 0 600 700 800 0 100 300 400 900 frequency (khz) power (mw) 200 600 500 700 800 lcs700 lcs701 lcs702 lcs703 lcs705 lcs708 pi-6184-112910 200 250 150 100 50 0 300 350 400 0 200 400 800 1000 1200 half-bridge voltage (v) capacitance (pf) 600 lcs700 lcs701 lcs702 lcs703 lcs705 lcs708 pi-6181-112910 400 500 300 20 100 0 600 700 800 0 2 6 8 16 18 frequency (khz) current (ma) 4 10 12 14 lcs700 lcs701 lcs702 lcs703 lcs705 lcs708 pi-6182-112910 400 500 300 20 100 0 600 700 800 0 2 6 8 16 frequency (khz) current (ma) 4 10 12 14 lcs700 lcs701 lcs702 lcs703 lcs705 lcs708 figure 27. v cc current vs. frequency. figure 29. control power vs. frequency. figure 28. v cch current vs. frequency. figure 30. half-bridge small signal capacitance vs. half-bridge voltage. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 24 lcs700-708 www.powerint.com pi-5639-031011 notes: 1. dimensioning and tolerancing per asme y14.5m-1994. 2. dimensions noted are determined at the outermost extremes of the plastic body exclusive of mold flash, tie bar burrs, gate burrs, and interlead flash, but including any mismatch between the top and bottom of the plastic body. maximum mold protrusion is 0.007 [0.18] per side. 3. dimensions noted are inclusive of plating thickness. 4. does not include interlead flash or protrusions. 5. controlling dimensions in inches (mm). 0.628 (15.95) ref. 0.019 (0.48) ref. 0.060 (1.52) ref. 10 ref. all around 0.021 (0.53) 0.019 (0.48) 0.048 (1.22) 0.046 (1.17) 0.027 (0.70) 0.023 (0.58) 0.038 (0.97) 0.076 (1.93) 0.118 (3.00) 0.029 dia hole 0.062 dia pad 0.020 (0.50) 0.016 (0.41) ref. detail a 0.118 (3.00) 0.140 (3.56) 0.120 (3.05) 0.081 (2.06) 0.077 (1.96) 13 0.016 (0.41) 0.011 (0.28) 0.020 m 0.51 m c 3 0.290 (7.37) ref. 0.047 (1.19) c 0.038 (0.97) 0.056 (1.42) ref. 1 3 4 5 6 7 8 9 10 11 13 14 16 0.653 (16.59) 0.647 (16.43) 2 0.325 (8.25) 0.320 (8.13) 2 a b pin 1 i.d. 0.214 (5.44) ref. 0.076 (1.93) 0.012 (0.30) ref. 0.210 (5.33) ref. 0.207 (5.26) 0.187 (4.75) 13 0.024 (0.61) 0.019 (0.48) 0.010 m 0.25 m c a b 4 3 0.519 (13.18) ref. front view side view back view detail a (scale = 9 ) pcb foot print end view esip-16c (h package) dimensions in inches, (mm). all dimensions are for reference. www.datasheet.co.kr datasheet pdf - http://www..net/
rev. b 062011 25 lcs700-708 www.powerint.com part ordering information ? hiper product family ? lcs series number ? package identifer h plastic esip-16c ? pin finish g halogen free and rohs compliant ? tape & reel and other options blank standard confgurations lcs 700 h g - tl www.datasheet.co.kr datasheet pdf - http://www..net/
for the latest updates, visit our website: www.powerint.com power integrations reserves the right to make changes to its products at any time to improve reliability or manufacturability. power integrations does not assume any liability arising from the use of any device or circuit described herein. power integrations makes no warranty herein and specifically disclaims all warranties including, without limitation, the implied warranties of merchantability, fitness for a particular purpose, and non-infringement of third party rights. patent information the products and applications illustrated herein (including transformer construction and circuits external to the products) may be covered by one or more u.s. and foreign patents, or potentially by pending u.s. and foreign patent applications assigned to power integrations. a complete list of power integrations patents may be found at www.powerint.com. power integrations grants its customers a license under certain patent rights as set forth at http://www.powerint.com/ip.htm. life support policy power integrations products are not authorized for use as critical components in life support devices or systems without the express written approval of the president of power integrations. as used herein: 1. a life support device or system is one which, (i) is intended for surgical implant into the body, or (ii) supports or sustains life, and (iii) whose failure to perform, when properly used in accordance with instructions for use, can be reasonably expected to result in signifcant injury or death to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. the pi logo, topswitch, tinyswitch, linkswitch, dpa-switch, peakswitch, capzero, senzero, linkzero, hiperpfs, hipertfs, hiperlcs, qspeed, ecosmart, clampless, e-shield, filterfuse, stakfet, pi expert and pi facts are trademarks of power integrations, inc. other trademarks are property of their respective companies. ?2011, power integrations, inc. power integrations worldwide sales support locations world headquarters 5245 hellyer avenue san jose, ca 95138, usa. main: +1-408-414-9200 customer service: phone: +1-408-414-9665 fax: +1-408-414-9765 e-mail: usasales@powerint.com china (shanghai) rm 1601/1610, tower 1, kerry everbright city no. 218 tianmu road west, shanghai, p.r.c. 200070 phone: +86-21-6354-6323 fax: +86-21-6354-6325 e-mail: chinasales@powerint.com china (shenzhen) rm a, b & c 4th floor, block c, electronics science and technology bldg., 2070 shennan zhong rd, shenzhen, guangdong, china, 518031 phone: +86-755-8379-3243 fax: +86-755-8379-5828 e-mail: chinasales@powerint.com germany rueckertstrasse 3 d-80336, munich germany phone: +49-89-5527-3910 fax: +49-89-5527-3920 e-mail: eurosales@powerint.com india #1, 14th main road vasanthanagar bangalore-560052 india phone: +91-80-4113-8020 fax: +91-80-4113-8023 e-mail: indiasales@powerint.com italy via de amicis 2 20091 bresso mi italy phone: +39-028-928-6000 fax: +39-028-928-6009 e-mail: eurosales@powerint.com japan kosei dai-3 bldg. 2-12-11, shin-yokomana, kohoku-ku yokohama-shi kanagwan 222-0033 japan phone: +81-45-471-1021 fax: +81-45-471-3717 e-mail: japansales@powerint.com korea rm 602, 6fl korea city air terminal b/d, 159-6 samsung-dong, kangnam-gu, seoul, 135-728, korea phone: +82-2-2016-6610 fax: +82-2-2016-6630 e-mail: koreasales@powerint.com singapore 51 newton road #15-08/10 goldhill plaza singapore, 308900 phone: +65-6358-2160 fax: +65-6358-2015 e-mail: singaporesales@powerint.com taiwan 5f, no. 318, nei hu rd., sec. 1 nei hu dist. taipei, taiwan 114, r.o.c. phone: +886-2-2659-4570 fax: +886-2-2659-4550 e-mail: taiwansales@powerint.com europe hq 1st floor, st. jamess house east street, farnham surrey gu9 7tj united kingdom phone: +44 (0) 1252-730-141 fax: +44 (0) 1252-727-689 e-mail: eurosales@powerint.com applications hotline world wide +1-408-414-9660 applications fax world wide +1-408-414-9760 revision notes date b initial release 06/20/11 www.datasheet.co.kr datasheet pdf - http://www..net/

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